n-channel enhancement mode power mosfet 0 9/06 /2007 rev.1.00 www.siliconstandard.com 1 SSM03N70GH/gj product summ ary repetitive avalanche rated fast switching speed simple drive requirement descri ption the to-252 package is universally preferred for all commercial- industrial su rface mount application s and suited f or ac/dc c onverters. the through-hole version (ssm03 n70gh/gj) is available fo r low-profile application s . absolute m a xi mum ratings bv dss 600v r ds(on) 3.6 i d 3.3a g d s g d s to-252(h) g d s to-251(j) symbol units v ds drain-source voltage v v gs gate-source voltage v i d @t c =25 continuous drain current, v gs @ 10v a i d @t c =100 continuous drain current, v gs @ 10v a i dm pulsed drain current 1 a p d @t c =25 total power dissipation w w/ e as single pulse avalanche energy 2 mj i ar avalanche current a e ar repetitive avalanche energy mj t stg t j operating junction temperature range t hermal data symbol value units rthj-c thermal resistance junction-case max. 2.8 /w rthj-a thermal resistance junction-ambient max. 110 /w parameter 3.3 parameter -55 to 150 85 30 3.3 storage temperature range linear derating factor -55 to 150 0.36 45 13.2 rohs-compliant
0 9/06 /2007 rev.1.00 www.siliconstandard.com 2 SSM03N70GH/gj electri c al characteristi cs @ t j =25 o c ( unless otherwise specified ) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua 600 - - v ? bv dss / ? t j breakdown voltage temperature coefficient reference to 25 , i d =1ma - 0.6 - v/ r ds(on) static drain-source on-resistance v gs =10v, i d =1.6a - - 3.6 v gs(th) gate threshold voltage v ds =v gs , i d =250ua 2 - 4 v g fs forward transconductance v ds =10v, i d =1.6a - 2 - s i dss drain-source leakage current (t j =25 o c) v ds =600v, v gs =0v - - 10 ua drain-source leakage current (t j =150 o c) v ds =480v , v gs =0v - - 100 ua i gss gate-source leakage v gs =30v - - 100 na q g total gate charge 3 i d =3.3a - 11.4 - nc q gs gate-source charge v ds =480v - 3.1 - nc q gd gate-drain ("miller") charge v gs =10v - 4.2 - nc t d(on) turn-on delay time 3 v dd =300v - 8.4 - ns t r rise time i d =3.3a - 6 - ns t d(off) turn-off delay time r g =10 , v gs =10v - 17.7 - ns t f fall time r d =91 - 5.9 - ns c iss input capacitance v gs =0v - 600 - pf c oss output capacitance v ds =25v - 45 - pf c rss reverse transfer capacitance f=1.0mhz - 4 - pf s ource-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 3 i s =3a, v gs =0v - - 1.5 v t rr reverse recovery time 2 i s =3a, v gs =0v, - 422 - ns q rr reverse recovery charge di/dt=100a/s - 2580 - nc notes: 1.pulse width limited by safe operating area. 2.starting t j =25 o c , v dd =50v , l=15mh , r g =25 , i as =3a. 3.pulse width < 300us , duty cycle < 2%.
0 9/06 /2007 rev.1.00 www.siliconstandard.com 3 SSM03N70GH/gj fig 1. typical output characteristics fig 2. typical output characteristics fig 3. normalized bv dss v.s. junction fig 4. normalized on-resistance temperature v.s. junction temperature fi g 5. forward characteristic o f fig 6. gate threshold voltage v.s. reverse diode junction temperature 0.1 0.5 0.9 1.3 1.7 2.1 2.5 -50 0 50 100 150 t j , junction temperature ( o c) n o rmalize d r ds(on) i d =1.6a v g =10v 0.8 0.9 1.0 1.1 1.2 -50 0 50 100 150 t j , junction temperature ( o c) n o rmalize d bv dss (v ) 0 1 2 3 4 0 5 10 15 20 25 v ds , drain-to-source voltage (v) i d , dr a i n c u r r e nt (a ) t c =25 o c 5.0v 4.5v v g =4.0v 10v 6.0v 0 1 1 2 2 0 5 10 15 20 25 v ds , drain-to-source voltage (v) i d , dr a i n c u r r e nt (a ) t c =150 o c v g =3.5v 4.5v 4.0v 10v 5.0v 0.01 0.1 1 10 100 0.1 0.3 0.5 0.7 0.9 1.1 1.3 v sd , source-to-drain voltage (v) i s (a ) t j = 25 o c t j = 150 o c 0 1 2 3 4 5 -50 0 50 100 150 t j , junction temperature ( o c) v gs(t h) (v )
0 9/06 /2007 rev.1.00 www.siliconstandard.com 4 SSM03N70GH/gj fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform 0.01 0.1 1 10 100 1 10 100 1000 10000 v ds , drain-to-source voltage (v) i d (a ) t c =25 o c single plude 10us 100us 1ms 10ms 100ms 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 10 t , pulse width (s) n o rmalize d t h e rmal re spon se ( r th jc ) p dm duty factor = t/t peak t j = p dm x r thjc + t c t t 0.02 0.01 0.05 0.1 0.2 duty=0.5 single pulse 0 2 4 6 8 10 12 14 16 04 8 1 2 1 6 q g , total gate charge (nc) v gs , g a te to s o u rc e voltage ( v ) i d =3.3a v ds =480v 1 100 10000 1 5 9 1 31 72 1 2 52 9 v ds , drain-to-source voltage (v) c ( p f) f =1.0mh z c iss c oss c rss t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 10v q gs q gd q g charge
SSM03N70GH/gj 0 9/06 /2007 rev.1.00 www.siliconstandard.com 5 information furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties.
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